ABSTRACT - The FFT is one of the most widely used algorithms for calculating the Discrete Fourier Transform (DFT) owing to its efficiency in reducing computation time. Fast Fourier Transform (FFT) has been used in a wide range of applications, such as wide-band mobile digital communication system based on Orthogonal Frequency Division Multiplexing (OFDM) principle, where the system implementation is only feasible when the equipment complexity and power consumption are greatly reduced by utilizing a realtime FFT transformer to replace the bank of (de)modulators for each individual sub-carriers. FFT, as an efficient algorithm to compute the Discrete Fourier Transform (DFT), is one of the most important operations in modern digital signal Processing and communication systems. Contact:
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ABSTRACT - This article describes an 8-bit RISC processor design using Verilog Hardware Description Language (HDL) on FPGA board. The proposed processor is designed using Harvard architecture, having separate instruction and data memory. The salient feature of proposed processor is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. Another important feature is that instruction set contains only 34 instructions, which is very simple, easy to learn and compact. The proposed processor has 8-bit ALU, Two 8-bit I/O ports, serial-in/serial-out ports, Eight 8-bit general-purpose registers, 4-bit flag register and priority based three vectored interrupts. Another advantage of the proposed processor is that it can execute programs with up to 262,144 instructions long, such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan 3E Starter Board FPGA with 0.0517μs instruction cycle. Contact:
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ABSTRACT - To achieve the goal of secure communication, cryptography is an essential operation. Many applications, including health-monitoring and biometric data based recognition system, need short-term data security. To design short-term security based applications, there is an essential need of high-performance, low cost and area efficient VLSI implementation of lightweight ciphers. Data encryption standard (DES) is well-suited for the implementation of low-cost lightweight cryptography applications. In this paper, we propose an efficient VLSI archi3tecture for DES algorithm based encryption/decryption engine. Depending upon the encryption/decryption needs, the same set of architecture performs both encryption and decryption operations. In the implementation of DES algorithm, a chain of multiplexer-based architecture is used to implement the substitution operations (SBoxes). The proposed architecture is modeled in the VHDL design language and synthesized in the Xilinx Virtex-5 xc5vfx70t field-programmable gate array (FPGA) device. Hardware synthesis result shows that the proposed design utilizes only 1.07 % slice LUTs, 0.31 % slice registers and 29.22 % of bonded IOBs of the FPGA device fabric. Contact:
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ABSTRACT - Experimental realism of wireless testbeds along with control and repeatability of experiments are some of the prominent fundamental barriers faced by researchers. To overcome these barriers, we are developing a wireless channel emulator that emulates the physical layer and brings about the realism and repeatability in our experiments. Channel emulators are generally used for testing air interface in Wireless Communication. In a laboratory test environment channel emulators replicate real world communication channel that exists between a transmitter and a receiver, it does so by providing a faded representation of the signal transmitted by the transmitter to the receiver inputs. It can be seen that emulator based approach helps us in understanding the performance of real world wireless channels. It also enables us to test our research in an operational wireless network, along with the advantages of a controlled experimental lab environment. Contact:
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ABSTRACT - A large number of computer applications(like Computer Graphics, Control Systems, Modeling System, Simulators etc.) needed floating point arithmetic. However, most of the presently available methods are slow and inefficient because of sequential design however the recent development in the field of programmable logic devices such as FPLA and CPLD opens the new area of parallel and high speed floating point designs. Considering that the synchronous architectures requires that that all clock events happen at the same time over the complete circuit which it not possible due to clock skew also the latency and throughput of the circuit are directly linked to the worst-case delay of the slowest element which increases the delay. Hence this paper presents self-timed carry look ahead adder based implementation of IEEE 754 32 bit floating point multiplier for FPGA devices. The simulation results shows that the proposed design has lower latency than synchronous design as well as lower power requirements. Contact:
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ABSTRACT - In this paper, an efficient mapping of the pipeline single-path delay feedback (SDF) fast Fourier transform (FFT) architecture to field-programmable gate arrays (FPGAs) is proposed. By considering the architectural features of the target FPGA, significantly better implementation results are obtained. This is illustrated by mapping an R22SDF 1024-point FFT core toward both Xilinx Virtex-4 and Virtex6 devices. The optimized FPGA mapping is explored in detail. Algorithmic transformations that allow a better mapping are proposed, resulting in implementation achievements that by far outperforms earlier published work. For Virtex-4, the results show a 350% increase in throughput per slice and 25% reduction in block RAM (BRAM) use, with the same amount of DSP48 resources, compared with the best earlier published result. The resulting Virtex-6 design sees even larger increases in throughput per slice compared with Xilinx FFT IP core, using half as many DSP48E1 blocks and less BRAM resources. The results clearly show that the FPGA mapping is crucial, not only the architecture and algorithm choices. Contact:
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ABSTRACT - DC-DC converters are electronic devices. It’s used whenever there is a need to change DC electrical power from one voltage level to another, in an efficient manner. Unlike an AC voltage DC cannot be just stepped down or stepped up. DC-DC convertor is DC equivalent to a Transformer. Typical applications of DC-DC converters are where 24V (which is used for a 24V device) DC must be stepped down to 12V DC to operate a 12V device. Similarly 12V-3V DC & 5V-2V conversion. Contact:
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ABSTRACT - Because of rich applications, smart operating systems on cell phones are now being migrated to home appliances like televisions. However, applications that are originally designed to be operated by touch screen are not suitable for televisions with these systems. This paper presents a method to manipulate applications with infrared remote control instead of touch screen on televisions without rewriting the code of these applications or adding extra expense on hardware. The principle of the method is to map keystroke events on the remote control to virtual touch based events according to specific mapping relationship corresponding to each application. Since the mapping relationship is various in each scene within one application, scenes should be recognized with feature information before the mapping process. The feature information and the mapping relationship in each scene have been set up prior to running of the application. When one application is running, the current scene of the application could be identified by scene recognition algorithm, the mapping relationship related to the current scene is able to be acquired, and then keystrokes on the remote control would be mapped to touch based events. The proposed method is tested on a smart television platform, and the result indicates the method can operate most applications by remote control, while the input response delay brought by the event mapping is negligibly less than one millisecond. Contact:
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ABSTRACT - The hardware implementation of deep neural networks (DNNs) has recently received tremendous attention: many applications in fact require high-speed operations that suit a hardware implementation. However, numerous elements and complex interconnections are usually required, leading to a large area occupation and copious power consumption. Stochastic computing (SC) has shown promising results for low-power area-efficient hardware implementations, even though existing stochastic algorithms require long streams that cause long latencies. In this paper, we propose an integer form of stochastic computation and introduce some elementary circuits. We then propose an efficient implementation of a DNN based on integral SC. The proposed architecture has been implemented on a Virtex7 field-programmable gate array, resulting in 45% and 62% average reductions in area and latency compared with the best reported architecture in the literature. We also synthesize the circuits in a 65-nm CMOS technology, and we show that the proposed integral stochastic architecture results in up to 21% reduction in energy consumption compared with the binary radix implementation at the same misclassification rate. Due to fault-tolerant nature of stochastic architectures, we also consider a quasi-synchronous implementation that yields 33% reduction in energy consumption with respect to the binary radix implementation without any compromise on performance. Contact:
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ABSTRACT - In this paper we present an approach for to create a Sixth Sense device which works of the principles of gesture recognition and image processing to capture, zoom(in and out) and toggle pictures with ease just by the help of colored caps/LED worn on the fingertips of the user. Contact:
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ABSTRACT - The potential threats coming from viruses, malware, adware and hackers are constant. The last couple of years have seen many massive global companies become hacked and compromised. In some cases, this has led to the theft of sensitive and private information including bank details, addresses etc. with a strong security system in place these intrusions can be stopped before they get anywhere near a company’s private data. This is not just important in terms of confidentiality but for avoiding the expensive fines that are imposed on companies that do not successfully protect customer’s data. The project is an authentication system that validates user for accessing the system only when they have input correct password. The project involves three levels of user authentication. There are varieties of password systems and authentications available. It contains three logins having three different kinds of systems. First one is given the access through the face recognition. Second type of authentication is scan the finger print of the user. By using these three level authentication, there is less chance for hacking. Contact:
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